(a) Field of the Invention
The present invention relates to a latch circuit for latching a pair of complementary data signals and, more particularly, to a latch circuit which responds to a pair of complementary clock signals to latch a pair of complementary data signals.
(b) Description of the Related Art
A latch circuit is known which responds to a pair of complementary clock signals to latch and transfer a pair of input complementary data signals. A CMOS circuit is generally used for such a latch circuit. FIG. 6 shows a conventional latch circuit, which is described in Patent Publication JP-A-2001-21786.
The latch circuit of FIG. 6 includes a sample section 10C activated by one of a complementary clock signals ICT and ICB to sample a pair of input complementary data signals IT and IB, and a latch section 20C activated by the other of the complementary clock signals ICT and ICB to latch the complementary data signals sampled by the sample section 10C and deliver output complementary data signals OT and OB to a next stage circuit.
The sample section 10C includes n-channel transistors (nMOSFETs) Q1 and Q4 each receiving clock signal ICB at the gate thereof, nMOSFETs Q2 and Q7 each receiving data signal IT at the gate thereof, and nMOSFETs Q3 and Q6 each receiving data signal IB at the gate thereof. The nMOSFETs Q2 and Q3 are serially connected to form a serial current path, which is connected in parallel with another serial current path formed by nMOSFETs Q6 and Q7 to thereby form a parallel current path. The parallel current path is connected to a high-potential power source line VCC via a MOSFET Q1, and to a low-potential power source line (ground line) GND via a MOSFET Q4. The sample section 10C delivers complementary data signals TC and BC through the source of MOSFET Q2, or sample output node N1, and the source of MOSFET Q6, or sample output node N2, respectively, to the latch section 20C.
The latch section 20C includes pMOSFETs Q9 and Q13, and nMOSFETs Q10 to Q12, Q14 and Q15. MOSFETs Q9 to Q12 are connected between the power source line VCC and the ground line GND in this order as viewed from the power source line VCC. MOSFETs Q13 to Q15 are connected between the power source line VCC and the drain of nMOSFET Q12 in this order as viewed from the power source line VCC. The gates of MOSFETs Q9 and Q13 receive complementary data signals BC and TC, respectively, from the sample section 10C, whereas the gate of nMOSFET Q12 receives clock signal ICT. The gate of pMOSFET Q9 is further connected to sample output node N2 connecting MOSFETs Q14 and Q15 in series, and the gate of nMOSFET Q13 is connected to sample output node N1 connecting MOSFETs Q10 and Q11 in series. The latch circuit of FIG. 6 delivers output complementary data signals OT and OB through the output node (latch output node) N3 connecting MOSFETs Q9 and Q10 in series, and the output node (latch output node) N4 connecting MOSFETs Q13 and Q14 in series, respectively. The gate of MOSFET Q11 is connected to latch output node N4 delivering therethrough output data signal OB, whereas the gate of MOSFET Q15 is connected to latch output node N3 delivering therethrough output data signal OT.
MOSFETs Q2, Q3, Q6, and Q7 of the sample section 10C constitute data input transistors for receiving input complementary data signals IT and IB and transmitting the same as complementary data signals TC and BC, whereas MOSFETs Q1 and Q4 of the sample section 10C constitute sample-section activating transistors for activating the data input transistors of the sample section 10C during a sample period of the latch circuit. MOSFETs Q9 and Q11 of the latch section 20C constitute a first inverter whereas MOSFETs Q13 and Q15 constitute a second inverter, wherein both the inverters are connected so that the input of each inverter is connected to the output of the other inverter. MOSFETs Q10 and Q14 constitute voltage-liming transistors which reduce the power source potential, and MOSFET Q12 constitutes a latch-section activating transistor for activating the latch section 20C during a hold period of the latch circuit.
In operation, the sample section 10C is activated to operate for sampling during a sample period wherein clock signals ICT and ICB assume a low level and a high level, respectively, thereby sampling the input complementary data signals IT and IB. The latch section 20C is activated during a hold period after clock signal ICT rises to a high level, to thereby latch complementary data signals TC and BC through sample output nodes N1 and N2 from the sample section 10C and deliver output complementary data signals OT and OB through latch output nodes N3 and N4 to the next stage circuit.
Thereafter, in the next sample period when clock signals ICT and ICB again assume a low level and a high level, respectively, the sample section 10C is again activated to latch new input complementary data signals IT and IB, whereby the latch section 20C again latches complementary data signals TC and BC through sample output nodes N1 and N2 in the next hold period.
If the sample section 10C samples new input complementary data signals having a data different from the data of the previous input complementary data signals, the electric charge stored on the latch output node N3 or N4 then assuming a high level is discharged via MOSFET Q12 of the latch section 20C toward the ground line GND upon the signal inversion of the output complementary data signals OT and OB, thereby allowing the output node N3 or N4 to fall toward a low level. At the same time, electric charge is injected to the latch output node N4 or N3 then assuming a low level from the power source line VCC via MOSFETs Q9 and Q13, thereby allowing the latch output node N4 or N3 to rise toward a high level.
It is to be noted that the discharge and injection of the electric charge concurrently occur during the sample period wherein the sample section 10C is activated. This causes a large energy burden on the power source lines VCC and GND, whereby the time length needed for the discharge and injection of the electric charge increases. The increased time length for the discharge and injection of the electric charge increases the time length needed for the signal inversion of the latch output node N3 and N4, thereby increasing the dead zone of the latch circuit including a setup time and a hold time thereof. This may cause a malfunction of the latch circuit in the signal transmission depending on the delivery timing of the input complementary data signals.